1. Field of the Invention
The present invention relates to methods of fabricating semiconductor devices. In particular, the present invention relates to the steps associated with the fabrication of Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) structures. More particularly, the present invention relates to those aspects of the fabrication of BiCMOS structures involving the formation of the insulative oxide layer under the gates of the MOS transistors and the processes associated with adjusting the threshold voltage for such transistors. The present invention provides for fabrication of the gate oxide and the threshold adjustment with little impact on the integrity of the gate oxide as part of a BiCMOS fabrication process.
2. Description of the Prior Art
In an effort to create increasingly faster semiconductor devices that consume less power, it is a goal in the semiconductor industry to create increasingly smaller integrated circuit (IC) devices. To that end, the steps associated with the fabrication of IC devices are becoming more critical and complex. With increasing complexity and criticality comes significant potential for a decrease in productivity, including greater fabrication costs and lower device yield. It is therefore a continuing goal in this field to minimize fabrication steps and the time and errors associated therewith.
Improvements are sought in all areas of semiconductor fabrication, particularly so in advanced processes. In the field of advanced BiCMOS devices, the integration of the steps associated with the formation of bipolar devices and MOS devices creates the type of complexity that requires considerable fabrication coordination. The addition of more masks, implants, depositions, etchings, and the like for advanced BiCMOS processing increases the costs associated with raw materials, capital equipment, and direct and indirect labor obligations. Moreover, modifications made in some steps are likely to affect fabrication results related to subsequent steps. It is therefore important to take into account the entirety of the integrated fabrication process when creating BiCMOS devices.
One area in particular in which fabrication integrity must be maintained is in the formation of the active areas of the transistors. With particular regard to the N-type and P-type MOS transistors, it is important to ensure that the gate oxide layer used to electrically isolate the source, drain, and channel regions from the gate not be compromised during subsequent fabrication steps. That goal can be difficult to achieve when during subsequent steps conductive ions are implanted into active areas in order to establish a reliable turn-on potential or threshold voltage of the transistor. However, it is important to ensure certainty in the operation of the transistor so the transistor's threshold potential must be well defined and so the introduction of the conductive ions is critical.
Resolution of those seemingly opposite goals may be possible when the fabrication process is restricted to formation only of MOS structures. However, it can be particularly difficult in a BiCMOS process in which certain fabrication steps are applicable for one type of active device, e.g., a bipolar transistor, but not for another, e.g., a PMOS transistor. The fabrication of MOS transistors with high gate oxide integrity and suitable threshold voltage adjustment is an important component of the BiCMOS process but is not an isolated part of that process. Therefore, a BiCMOS process that resolves gate oxide integrity and voltage adjust would be of particular use.
In general, there are approximately 20 significant processing or mask steps associated with a BiCMOS fabrication process related to the present invention. Those steps, identified by the mask designations noted, are substantially as follows:
______________________________________ Mask No. Mask Function ______________________________________ 1.0 N+ Buried Layer Mask 2.0 P+ Buried Layer Mask 3.0 Isolation Oxide Definition Mask 4.0 Sink Implant Mask 5.0 Channel Stop and PWell Mask 6.0 P-type Anti-punch Through & Threshold Adjust Mask 7.0 N-type Anti-punch Through & Threshold Adjust Mask 8.0 Base Definition Mask 9.0 N+ Poly Layer Mask 10.0 Polycrystalline Silicon Gate Definition Mask 11.0 N LDD Mask 12.0 P LDD Mask 13.0 P+ Source/Drain Definition Mask (PMOS) 14.0 N+ Source/Drain Definition Mask (NMOS) 15.0 Source/Drain Definition Mask (NMOS) 16.0 Contact Definition Mask 17.0 METAL 1 (M1) Definition Mask 18.0 VIA Definition Mask 19.0 METAL 2 (M2) Definition Mask 20.0 Bond Pad Definition Mask ______________________________________
Of course, each one of the noted steps includes a plurality of sub-steps, some more so than others. In fact, there are more than one hundred steps associated with the formation of a BiCMOS structure, each of which is important to creation of high quality, reliable devices.
While there are many steps and stages associated with the complete fabrication of an integrated circuit on a semiconductor wafer, the ones set out above and described briefly herein are directly applicable to the present invention. Of particular interest in regard to the present invention are the steps related to formation of the insulative gate oxide and subsequent adjustment of the conductivity of the active regions of the transistor device. Prior to addressing important aspects of the formation of those two areas of a BiCMOS device, the fabrication process will be described briefly in relation to the noted mask steps.
Initially, for a BiCMOS device including an NPN bipolar transistor, a buried collector layer is created on a P type substrate of semiconductor material using conventional fabrication sequences. This is accomplished by introducing, such as by implantation, an N concentration of relatively slow diffusing N type atoms to form an underlying layer for subsequent retrograde diffusion. Next, an "NWell" and a "PWell" are created on the P type substrate of semiconductor material, using conventional fabrication sequences. This is accomplished by introducing, such as by implantation, respectively, an N concentration of relatively fast-diffusing N type atoms to form an NWell "bed" for the PMOS structure, and a P concentration of relatively fast-diffusing P type atoms to form a PWell "bed" for the NMOS structure. Additionally, the P type atoms are introduced into area adjacent to the buried collector layer and the NWell bed to form channel stops for isolation of adjacent active areas. The channel stops isolate the wells from parasitic MOS effects caused by adjacent structures.
After NWell and PWell bed introduction into the substrate, an epitaxial layer in the form of single crystal N type semiconductor material in an N.sup.- concentration is formed over the buried collector layer and both well beds. Subsequent conventional diffusion processing drives the NWell and PWell atoms in retrograde concentrations to the surface of the epitaxial layer. The slower diffusing collector layer atoms move toward that surface but do not reach it. Next, isolation oxide layers are formed about the transistor structures by conventional mask, etch, and formation sequences so as to isolate them from adjacent structures. Field oxide regions are formed above the isolation regions to aid in the isolation of adjacent structures at the surface of the epitaxial layer. A collector sink of relatively fast-diffusing N type atoms is then introduced into the epitaxial layer above a portion of the buried collector layer for subsequent collector development.
Continuing with the summary description of the BiCMOS process of interest, formation of the MOS transistor structures requires the fabrication of the gate, source, and drain components of the NMOS and PMOS transistor structures. Additionally, formation of the bipolar transistor structures requires the fabrication of the base, emitter and collector components. For the MOS structures, channel regions for the PMOS and NMOS transistor structures are doped with appropriate levels of conductive ions to tailor threshold voltage (Vt) and anti-punch through (APT) protection characteristics of the device to be formed. Subsequently, the dielectric gate oxide layer is formed after an epitaxial layer surface clean and a thermal processing to be described briefly herein. The gates are then formed of a polycrystalline layer of semiconductor material, using a well-known mask, etch, and deposition sequence. This "polysilicon layer" is formed on the surface of the respective wells, but is separated from the well surfaces by the underlying gate oxide layer. In the BiCMOS process, the polysilicon layer is used to form polycrystalline silicon gates of the MOS transistors and a polysilicon emitter of the bipolar transistor upon suitable subsequent implanting.
The gate oxide layer insulates the gate of the particular MOS transistor structure from the source, the drain, and the channel lying therebetween. The integrity of this gate oxide layer must be maintained throughout the integrated fabrication process so as to ensure effective transistor operation. It is preferably relatively thin so as to produce good MOS transconductance, to reduce Drain-Induced Barrier Lowering (DIBL) and short channel effects, and to increase source/drain punch-through voltage (BVDSS). It is to be noted that this oxide layer is also used in the BiCMOS process to form a dielectric layer for desired sink-based capacitances.
It is important to make the Vt adjust and corresponding APT protection regions of the MOS structures as thin and as well defined as possible in order to minimize DIBL and short-channel effects. Specifically, the APT profile must be well-defined in order to establish a distinct channel region while at the same time not extending past the source/drain junction depths that would otherwise increase drain-to-well capacitance. Doping concentrations and energies (when preferably performed by implant) must be carefully established in order to control the characteristics of this region of the MOS devices. However, thermal processing necessary to establish the gate oxide layer causes diffusion of the Vt/APT implants and therefore reduces the definition, and increases the thickness, of those regions.
In order to accommodate the different characteristics of the two types of transistors without degrading the quality of either, it has been determined that there are advantages in creating the polysilicon layer in two separate steps. This "split poly" process involves the introduction of a relatively thin layer of polycrystalline silicon over the gate oxide layer in a blanket deposition. On the bipolar side, relatively slow diffusing P type atoms in a P+ concentration are implanted into the surface of the epitaxial layer through the first polycrystalline silicon layer while the collector sink and CMOS active areas are protected by photoresist. It is important to note that the thickness of the first polycrystalline silicon layer must be well defined for purposes of the base implant. That is, if it is too thick the implant may not be driven deep enough to ensure desirable bipolar transistor characteristics.
After the base implant, the first polycrystalline silicon layer and the gate oxide layer are etched away on the surface of the base region only. The remaining active areas are again protected by photoresist. The next phase of the process involves the preparation of the wafer for development of the emitter and collector of the bipolar transistor structure and the gates, and source and drains of the CMOS transistor structures. Prior to undertaking the steps associated with that formation, the entirety of the surface of the first polysilicon layer is pre-cleaned with an acidic compound. A second polysilicon layer is then deposited on the cleaned surface of the first layer. The second polycrystalline silicon layer is substantially thicker than the first. The combination of the two polycrystalline silicon layers creates the pre-cursors for the gates of the CMOS transistor structures and the emitter of the bipolar transistor structure. That is, the two layers are electrode materials. Subsequent well-known steps are used to complete the remainder of the integrated circuitry.
In one particular split-poly BiCMOS fabrication process used by Fairchild Semiconductor Corporation of South Portland, Me., for the development of the gate oxide and first polycrystalline silicon layer formation first includes a standard pre-cleaning of the epitaxial layer for subsequent oxide growth. The gate oxide layer is then grown in an atmosphere of oxygen at a processing temperature on the order of 900.degree. C. Next, the first polycrystalline semiconductor layer in the split polycrystalline silicon process is formed using a chemical vapor deposition (CVD) at about 600.degree.-625.degree. C. The polycrystalline silicon is grown to a thickness of about 50 nanometers (nm) over a period of about two hours. However, that entire thermal processing adversely affects the Vt adjust and APT protection for the MOS transistor structures.
It has been determined that this first polycrystalline silicon layer must be at least as thick as noted in order to ensure that the subsequent surface cleaning of the first polycrystalline silicon layer will not be problematic for the underlying oxide layer. That cleaning relates to the removal of a photoresist layer required to ensure the definition of certain regions of the bipolar structure of the BiCMOS integrated circuitry. It is known that the acid cleaner use to remove that resist can migrate through interstices associated with the molecular orientation of the polycrystalline silicon. If permitted to move through to the gate oxide layer, the acid causes considerable damage to the insulative characteristics of that layer. Such damage often leads to reduce fabrication yields which have to this point been accepted as a standard cost involved in fabricating BiCMOS structures.
While the integrity of the gate oxide layer is of obvious concern, the degradation of the Vt and APT characteristics caused by the thermal development of that layer is also of increasing importance. To solve that particular problem, it has been suggested to introduce the dopants required for Vt adjust and APT protection after formation of the gate oxide layer. In that way, the diffusion of dopant in the region underlying the gate oxide layer caused by the prior thermal profile is significantly reduced. In an article entitled "A Novel CMOS Process Utilizing After-Gate-Implantation Process," Mikoshiba et al. describe the introduction of the threshold adjust dopant subsequent to gate oxide formation. However, the dopant is implanted through the very thick polysilicon layer, requiring very high doping energies to insure that the dopant reaches the appropriate depth under the oxide. This involves the use of very expensive equipment and may cause damage in other ways related to the implant energy required including, but not limited to, channeling problems. In that regard, the Mikoshiba process is not particularly applicable in many processes, including BiCMOS fabrication.
U.S. Pat. No. 5,407,839 issued to Maruo also suggests the introduction of Vt/APT controlling dopants subsequent to gate oxide formation. Maruo teaches such processing only in the context of MOS formation rather than in the more-critically-integrated process of BiCMOS fabrication. The Maruo process includes a suggestion to implant the dopant through the gate oxide but fails to address the importance of maintaining the integrity of the gate oxide layer during intermediary bipolar structure fabrication stages. That is, as previously indicated, the thickness of the first polycrystalline silicon layer must be well defined for purposes of the base implant. If it is too thick the base implant energy will need to be higher, creating a greater implant range and, thus, increasing basewidth and reducing bipolar speed, which is crucial for very high frequency operations, including in the multi-GHz range. That critical thickness is of significantly less importance in a CMOS-only device and so the thin poly layer may be made substantially thicker in order to protect the oxide integrity in subsequent etching steps without sacrificing electrical characteristics. Suggestions are made to use a split polysilicon layer to improve implant prospects, but Maruo fails to address the importance of keeping the first layer relatively thin without sacrificing oxide integrity in the BiCMOS process so that the base doping profile will be optimized.
Therefore, what is needed is an improved BiCMOS fabrication process that includes a reduction in yield loss associated with gate oxide integrity while also providing for an improved Vt/APT region of the MOS structures. What is also needed is such an improved BiCMOS fabrication process that involves the formation of the gate oxide layer and the split polycrystalline silicon layers such that the new structure includes a thinner first polycrystalline silicon layer without sacrificing gate oxide integrity (or base doping profile). Yet further, what is such an improved BiCMOS fabrication process that permits introduction of suitable Vt adjust and APT protection dopants without the need to use high energy implant equipment and without causing related channeling problems.